DipIETE – CS (OLD SCHEME)

 

Code: DC04                                                                 Subject: COMPUTER ORGANISATION

Flowchart: Alternate Process: JUNE 2010Time: 3 Hours                                                                                                     Max. Marks: 100

 

 

NOTE: There are 9 Questions in all.

·      Question 1 is compulsory and carries 20 marks. Answer to Q.1 must be written in the space provided for it in the answer book supplied and nowhere else.

·      Out of the remaining EIGHT Questions, answer any FIVE Questions. Each question carries 16 marks.

·      Any required data not explicitly given, may be suitably assumed and stated.

 

 

Q.1      Choose the correct or the best alternative in the following:                                  (210)

       

a.       How many address lines are needed to address each memory location in a  memory chip?  

 

                   (A)  10                                                (B)  11

(C)    8                                                 (D)  12

       

b.      In ________ addressing mode, operand is specified in the instruction itself.

 

(A)    Immediate                                    (B)  Autoincrement

(B)    Implied                                         (D)  Register

 

             c.   A shift register can be used for ___________.

 

(A)     parallel to serial conversion           (B)  serial to Parallel conversion

(C)  digital delay line                            (D)  all of these

       

             d.   Which of the following memories must be refreshed many times per second?

 

                   (A)  Static RAM                                  (B)  Dynamic RAM

                   (C)  EPROM                                      (D)  ROM

 

             e.   The memory placed between CPU and RAM is known as _________.

 

(A) Tape                                             (B)  Disk

(C)  CD                                              (D)  Cache

 

f.    The data-bus width of a  RAM is ________.

 

                   (A)   8                                                 (B)  10

(D)   12                                               (D)  16

 

 

 

 

             g.   In a JK flip-flop, input state is toggled when ________.

                  

(A)    J = 0, K = 0                                 (B)  J = 0, K = 1

(C)  J = 1, K = 0                                 (D)  J = 1, K = 1

 

             h.   The number 43 in 2’s complement representation using 8-bit representation is _________.

 

(A)     01010101                                    (B)  11010101

(C)  00101011                                    (D)  10101011

                  

             i.    Binary information can be stored in a __________.

                  

(A)    flip-flop                                        (B)   latch

(C)  register                                         (D)  all of these

 

             j.    The bus connected between the CPU and memory that permits transfer of information between main memory and the CPU is known as __________.

                  

                   (A) DMA bus                                      (B)  Memory bus

                   (C) Address bus                                  (D)  Control bus

 

 

Answer any FIVE Questions out of EIGHT Questions.

Each question carries 16 marks.

 

 

  Q.2     a.   A digital computer has a common bus system for 16 registers of 32 bits each. The bus is constructed with multiplexers.

 

                   (i)  How many selection inputs are there in each multiplexer?

                   (ii) What size of multiplexers is needed?

                   (iii) How many multiplexers are there in the bus?                                                 (8)

 

b.   Simplify the following Boolean function using K-maps:

      .                                                               (8)

     

  Q.3     a.  Design a 4-bit combinational circuit decremented using four full-adder circuits.                     (8)

 

             b.   A computer employs RAM chips of 256 X 8 and ROM chips of 1024 X 8. The computer system needs 2K bytes of RAM, 4K bytes of RAM and four interface units, each with four registers. A memory- mapped I/O configuration is used. The two highest order bits of the address bus are assigned 00 for RAM, 01 for ROM and 10 for interface registers.

 

                   (i)   How many RAM and ROM chips are needed?

                   (ii)  Give the address range in hexadecimal for RAM, ROM and interface.           (8)

 

 

 

  Q.4     a.   A computer uses a memory unit with 256K words of 32 bits each. A binary instruction code is stored in one word of memory. The instruction has four parts: an indirect bit, an operation code, a register code part to specify one of 64 registers and an address part.

 

                   (i)   How many bits are there in the operation code, the register code part                           and the address part?

                   (ii)  Draw the instruction word format and indicate the number of bits in                  

                          each part.

                   (iii) How many bits are there in the data and address inputs of the memory?         (8)

 

             b.   What are the basic differences between a branch instruction, a call subroutine instruction, and program interrupt?                                             (8)

 

  Q.5     a.   Explain cache memory and explain different types of mapping in cache memory.                 (8)

            

             b.   Write a program in assembly language to compare two words.                            (8)

 

  Q.6     a.   Draw the logic diagram of a 2 to 4 line decoder using NAND gates.  Give the truth table also.                                                                   (8)

 

b.   What are the advantages and disadvantages of assembly language over machine language?             (8)

       

  Q.7     a.   Briefly explain the instruction cycle.  Draw the flowchart also.                            (10)

                  

             b.   Describe the source-initiated strobe control for data transfer.                              (6)                      

 

  Q.8     a.   What do you understand by priority interrupt?  What are the various ways to handle them?  Explain.                                                                      (8)

 

             b.   Write a program to evaluate the following arithmetic statement using a general register computer with three address instructions.                            

                   X = [A – B + C * (D * E – F)] / [G + H * K].                                                   (8)

 

  Q.9     a.   What is virtual memory?  With the help of a diagram explain how a virtual address is mapped to a physical address?                                              (8)

                                                                                                                                                

             b.   Explain Booth’s algorithm and also specify an example for it.                               (8)