AMIETE – CS/IT (NEW SCHEME)   –   Code: AC58/AT58



Flowchart: Alternate Process: JUNE 2010Time: 3 Hours                                                                                                     Max. Marks: 100



NOTE: There are 9 Questions in all.

·      Question 1 is compulsory and carries 20 marks. Answer to Q.1 must be written in the space provided for it in the answer book supplied and nowhere else.

·      Out of the remaining EIGHT Questions, answer any FIVE Questions. Each question carries 16 marks.

·      Any required data not explicitly given, may be suitably assumed and stated.



Q.1       Choose the correct or the best alternative in the following:                                  (210)


             a. The Computational unit in a CPU of a computer is a _____ and the

                  basic building unit of it is ______.


                  (A)  Combinational Circuit, Parallel Adder.                                                                       

                  (B)  Combinational Circuit, Shift Register.  

                  (C)  Sequential Circuit, Parallel Adder.                                                                              

                  (D)  Sequential Circuit, Shift Register.

             b.  The performance equation of a CPU is , where T is the processor    time to execute a program; while N, S and R are respectively ____, ____ and________.


                  (A) Number of instructions, Average number of steps and number of                   Registers. 

                  (B) Number of Registers, Instruction size and Clock rate.  

                  (C) Number of instructions, Average number of steps and Clock rate.

                  (D) None of the above.


             c.  Using 2’s complement representation for an 8-bit number, the maximum                   range that can be represented is between __________ and _________.


                  (A) +128, – 128.           

                  (B) +127, – 128.

                  (C) +128, – 127.

                  (D) +256, – 256. 


            d.   An assembler directive appearing in the source file is characterized by ________.


                  (A) an equivalent op-code and appearing in the object file.

                  (B) an equivalent op-code and not appearing in the object file.

                  (C) no equivalent op-code but appearing in the object file.

                                                                              (D) no equivalent op-code and not appearing in the object file.




              e.                                                             Following are the examples of program development tools __________.


                  (A) Translator, loader.                          (B) Linker, de-bugger.

                  (C) Both (A) and (B).                           (D) Neither (A) nor (B).    


             f.   A sub-routine in any programming environment supports __________.


                  (A) Parameter passing.                         (B) Recursion.                                                      

                  (C) Nesting.                                          (D) All the above.


             g.  The initial contents of a stack pointer (SP) which gets decremented for write                  operation are FFFFh; if 5 words are written through PUSH operation,                                 then the SP contents are _______.


                  (A) FFFA                                              (B) FFF0h 

                  (C) FFF5h                                            (D) FFF9h


             h. A memory has 12 bit address bus. The maximum size of the memory unit is _________.


(A)  12                                                  (B)  

                  (C)                                               (D)


             i.   Which of the following operations results in a multiply by 2 operation?    


                  (A)  Logical right Shift Operation.        

                  (B)  Logical left Shift Operation.   

                  (C)  Arithmetic right Shift Operation.    

                                                                              (D)  All the above.


             j.   An N-bit carry look ahead adder has a delay that is approximately equal to                                ___________.


                  (A) Zero                                     

                  (B) NAverage propagation delay/stage  

                  (C) Average propagation delay/stage

                  (D) N2 Average propagation delay/stage



Answer any FIVE Questions out of EIGHT Questions.

Each question carries 16 marks.



  Q.2          a. What is a micro-computer? Explain with a neat block diagram the connections between a processor and the memory and role of each block.                                                                  (8)                                                                                (2+6)


             b.   Assuming a basic computer structure containing MDR, MAR, memory, ALU, etc. What are the steps needed to execute the instruction Add LocA, R0?  Specify in simple English.                                                                                                                                   (8)



 Q.3     a.  With a schematic diagram explain briefly the virtual memory address                     translation method based on concept of fixed length pages.                                                                             (8)


             b.  Write an assembly level program to display the contents of 10 bytes of main    memory starting from location LOC on a display unit. Assume each location                 contains two hex characters per byte and the contents of successive bytes should be displayed with an in-between space.         (8)  


   Q.4     a.   What are the addressing modes available in a computer? Explain with an example for each.                   (8)                                                                                                                           (11)


             b.   A memory has 16 bit address. 

                   A  array with each element occupying one word is stored in main memory locations 2300 through 2B27.  The elements are stored in column order. A(0,0), A(1,0)….. A(3,0), A(0,1),……. A(3, 9).

                   The following program is run

                   sum = 0;

                   for j = 0 to 9 do

                       sum = sum + A(0,j)


                   AVE = sum / 10;

                   for i = 9 down to 0 do

                           A(0, i) = A (0, i)/AVE


                   Which bits are used for tag in direct mapping cache and which bits are used for tag in set associative cache?  Show the contents of a direct mapped data cache when j takes the values 1, 3, 7 and when i take the values 6 and 4.                                               (8)


  Q.5     a.   Register R5 is used in a program to point to top-of-stack. Write a sequence of                                     instructions using Index, Auto-increment and Auto-decrement addressing modes                             to perform each of the following tasks;


                 (i)    Pop top two items off the stack, add them together and then push the                                         result onto the stack.

                 (ii)   Copy the fifth item from the top into register R3                        (4+4)


             b.   What do you understand by an Interrupt Service subroutine?                              (4)


             c.   A computer address bus with 16 lines ignores address lines A8 and A9 while reading a device address 7CA4h due to problem in the decoder. Find all possible addresses to which the device now responds.        (4)


   Q.6    a.  A certain processor has a set of 3 interrupt priority lines named as IPL0-2. Design and implement a priority encoder that accepts interrupt requests from 7 devices and generates a 3-bit priority code.  Draw the truth table.                                                   (8)


             b.   Design an interface circuit for connecting a 7-segment LED display as an output device on a synchronous bus.                                                                                                              (4+4)




  Q.7     a.   What do you mean by direct memory access (DMA)? Explain cycle stealing.     (10)


             b.   Using a neat diagram, explain how DMA controllers are used in a computer system.           (6)


  Q.8     a.   With a neat diagram explain how addition and subtraction can be realized            using a 4-bit adder. Explain the controlled inverter circuit in your diagram.                                                     (8)


             b.   Perform multiplication of the following 2’s complement numbers using Booth’s Algorithm where A is the multiplicand and B is the multiplier.

                        (i)  A= 010111 and B = 110110      (ii)  A= 110011 and B = 101100          (8)


Q.9     a.    Briefly explain the single bus architecture in a processor using a neat diagram.                     (8)       


             b.   Using single bus architecture diagram (as mentioned in Q.9a) write a sequence of operations to perform the following:


                   (i)  Add an immediate number NUM to R1.

                         (ii) Add the contents of memory location NUM to R1.                                  (8)