TYPICAL
QUESTIONS & ANSWERS
PART - I
OBJECTIVE
TYPE QUESTIONS
Each Question carries 2 marks.
Choose correct or the best
alternative in the following:
Q.1 The NAND gate output
will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
Ans: D
The NAND gate output
will be low if the two inputs are 11
(The Truth Table of
NAND gate is shown in Table.1.1)
|
X(Input) |
Y(Input) |
F(Output) |
|
0 |
0 |
1 |
|
0 |
1 |
1 |
|
1 |
0 |
1 |
|
1 |
1 |
0 |
Table 1.1 Truth Table
for NAND Gate
Q.2 What is the binary equivalent of the decimal number 368
(A) 101110000 (B) 110110000
(C) 111010000 (D) 111100000
Ans: A
The Binary equivalent of the Decimal
number 368 is 101110000
(Conversion
from Decimal number to Binary number is given in Table 1.2)
|
2 |
368 |
|
2 |
184
--- 0 |
|
2
|
92
--- 0 |
|
2 |
46
--- 0 |
|
2 |
23
--- 0 |
|
2 |
11
--- 1 |
|
2 |
5
--- 1 |
|
2 |
2
--- 1 |
|
2 |
1
--- 0 |
|
|
0
--- 1 |
Table 1.2 Conversion from Decimal number to Binary number
Q.3 The decimal equivalent of hex number 1A53 is
(A) 6793 (B) 6739
(C) 6973 (D) 6379
Ans: B
The decimal
equivalent of Hex Number 1A53 is 6739
(Conversion from Hex
Number to Decimal Number is given below)
1
A 5 3 Hexadecimal
16³
16² 16¹ 16° Weights
(1A53)16 = (1X16³) + (10 X 16²) +
(5 X 16¹) + (3 X 16º)
= 4096
+ 2560 +
80 + 3
=
6739
Q.4 
(A) C 1 D (B) D C 1
(C) 1 C D (D) 1 D C
Ans:
D
(734)8
= (1 D C)16
0001
│ 1101 │ 1100
1
D C
Q.5 The simplification of the Boolean
expression 
is
(A) 0 (B) 1
(C) A (D) BC
Ans:
B
The Boolean
expression is 
+ 
is equivalent to 1
+ = 
+
+
+
+
+
= A ++ C + + B +
= (A+)(B+)(C+) = 1X1X1 = 1
Q.6 The number of control lines for a 8 – to – 1 multiplexer is
(A) 2 (B) 3
(C) 4 (D) 5
Ans:
B
The
number of control lines for an 8 to 1 Multiplexer is 3
(The control signals are used to
steer any one of the 8 inputs to the output)
Q.7 How many Flip-Flops are required for mod–16 counter?
(A) 5 (B) 6
(C) 3 (D) 4
Ans:
D
The number of flip-flops is required for Mod-16 Counter is 4.
(For Mod-m Counter, we need N flip-flops where N is chosen
to be the smallest number for which 2N is greater than or equal to m. In this case 24 greater than or equal to 1)
Q.8 EPROM contents can be erased by exposing it to
(A) Ultraviolet rays. (B) Infrared rays.
(C) Burst of microwaves. (D) Intense heat radiations.
Ans:
A
EPROM contents can be erased by exposing it to Ultraviolet
rays
(The Ultraviolet light passes
through a window in the IC package to the EPROM chip where it releases stored
charges. Thus the stored contents are
erased).
Q.9 The hexadecimal number ‘A0’ has
the decimal value equivalent to
(A) 80 (B) 256
(C) 100 (D) 160
Ans: D
The
hexadecimal number ‘A0’ has the decimal value equivalent to 160
( A
0
161 160
= 10X161 + 0X160 =
160)
Q.10 The Gray code for decimal number 6 is equivalent to
(A) 1100 (B) 1001
(C) 0101 (D) 0110
Ans: C
The Gray code for decimal number 6 is equivalent to 0101
(Decimal number 6 is equivalent to binary number 0110)
+ + +
0 1 1 0
0 1 0 1
Q.11 The Boolean expression 
is equivalent to
(A) A + B (B)
(C) 
(D) A.B
Ans: A
The Boolean expression .B + A. + A.B is equivalent to
A + B
(.B + A. + A.B = B( + A ) + A.
= B +
A. {
( + A ) = 1}
= A + B {(B + A.) = B + A}
Q.12 The digital logic family which has
minimum power dissipation is
(A) TTL (B) RTL
(C) DTL (D) CMOS
Ans: D
The digital logic family which has minimum power dissipation is CMOS.
(CMOS being an unipolar logic family, occupy a very
small fraction of silicon Chip area)
Q.13 The
output of a logic gate is 1 when all its inputs are at logic 0. the gate is
either
(A) a NAND or an EX-OR (B) an OR or an EX-NOR
(C) an AND or an EX-OR (D) a NOR or an EX-NOR
Ans: D
The
output of a logic gate is 1 when all inputs are at logic 0. The gate is either
a NOR or an EX-NOR .
(The
truth tables for NOR and EX-NOR Gates are shown in fig.1(a) & 1(b).)
|
Input A
B |
Output Y |
|
0 0 |
1 |
|
0 1 |
0 |
|
1 0 |
0 |
|
1 1 |
0 |
|
Input A
B |
Output Y |
|
0 0 |
1 |
|
0
1 |
0 |
|
1 0 |
0 |
|
1 1 |
1 |
Fig.1(a) Truth Table for NOR Gate
Fig.1(b) Truth Table for EX-NOR Gate
Q.14 Data can be changed
from special code to temporal code by using
(A)
Shift registers (B) counters
(C) Combinational
circuits (D) A/D converters.
Ans: A
Data
can be changed from special code to temporal code by using Shift Registers.
(A
Register in which data gets shifted towards left or right when clock pulses are
applied is known as a Shift Register.)
Q.15 A ring counter consisting of five Flip-Flops will have
(A) 5 states (B) 10 states
(C) 32 states (D) Infinite states.
Ans: A
A ring counter
consisting of Five Flip-Flops will have 5 states.
Q.16 The
speed of conversion is maximum in
(A)
Successive-approximation A/D converter.
(B)
Parallel-comparative A/D converter.
(C)
Counter ramp A/D converter.
(D)
Dual-slope A/D converter.
Ans: B
The speed of conversion is maximum
in Parallel-comparator A/D converter
(Speed of conversion is maximum
because the comparisons of the input voltage are carried out simultaneously.)
Q.17 The 2’s complement of
the number 1101101 is
(A)
0101110 (B) 0111110
(C) 0110010 (D) 0010011
Ans: D
The
2’s complement of the number 1101101 is 0010011
(1’s complement of
the number 1101101 is 0010010
2’s
complement of the number 1101101is 0010010 + 1 =0010011)
Q.18 The
correction to be applied in decimal adder to the generated sum is
(A) 00101 (B) 00110
(C) 01101 (D) 01010
Ans: B
The
correction to be applied in decimal adder to the generated sum is 00110.
When the four bit sum is more
than 9 then the sum is invalid. In such cases, add +6(i.e. 0110) to the four bit sum to skip the six
invalid states. If a carry is generated when adding 6, add the carry to the next four bit group .
Q.19 When
simplified with Boolean Algebra (x + y)(x + z) simplifies to
(A) x (B) x + x(y + z)
(C) x(1 + yz) (D) x + yz
Ans: D
When
simplified with Boolean Algebra (x + y)(x + z) simplifies to x + yz
[(x
+ y) (x + z)] = xx + xz + xy + yz = x + xz
+ xy + yz (xx = x)
= x(1+z) + xy + yz = x + xy + yz {(1+z) = 1}
=
x(1 + y) + yz = x + yz {(1+y) = 1}]
Q.20 The
gates required to build a half adder are
(A) EX-OR gate and NOR gate (B) EX-OR gate and OR gate
(C) EX-OR gate and AND gate (D) Four NAND gates.
Ans: C
The gates required to build a half adder are EX-OR gate and AND gate
Fig.1(d)
shows the logic diagram of half adder.
Fig.1(d)
Logic diagram of Half Adder
Q.21 The
code where all successive numbers differ from their preceding number by single
bit is
(A) Binary
code. (B)
BCD.
(C) Excess
– 3. (D)
Gray.
Ans: D
The code where all successive numbers differ from their preceding number
by single bit is Gray Code.
(It is an unweighted
code. The most important characteristic of this code is that only a single bit
change occurs when going from one code number to next.)
Q.22 Which of the following is the fastest logic
(A) TTL (B) ECL
(C) CMOS (D) LSI
Ans: B
ECL is the fastest logic family of all logic
families.
(High speeds are
possible in ECL because the transistors are used in difference amplifier
configuration, in which they are never driven into saturation and thereby
the storage time is eliminated.
Q.23 If the input to T-flipflop is 100 Hz signal, the
final output of the three T-flipflops in cascade is
(A) 1000 Hz (B) 500 Hz
(C) 333 Hz (D) 12.5 Hz.
Ans: D
If the input to T-flip-flop is 100 Hz signal, the final output of the
three T-
flip-flops in
cascade is 12.5 Hz
{The final output of the three T-flip-flops in
cascade is
(T)
=
=
=12.5Hz}
Q.24 Which of the memory is volatile memory
(A) ROM (B) RAM
(C) PROM (D) EEPROM
Ans: B
RAM is a volatile memory
(Volatile memory means the
contents of the RAM get erased as soon as the
power goes off.)
Q.25 -8 is equal to signed binary
number
(A) 10001000 (B) 00001000
(C) 10000000 (D) 11000000
Ans: A
- 8 is
equal to signed binary number 10001000
(To represent negative numbers in the binary system, Digit 0 is used for
the positive sign and 1 for the negative sign. The MSB is the sign bit followed
by the magnitude bits. i.e.,
-
8 = 1000 1000
-
------- -----------------
Sign Magnitude
------- ---------------
Q.26 DeMorgan’s
first theorem shows the equivalence of
(A)
OR gate and Exclusive OR gate.
(B)
NOR gate and Bubbled AND gate.
(C)
NOR gate and NAND gate.
(D)
NAND gate and NOT gate
Ans: B
DeMorgan’s
first theorem shows the equivalence of NOR gate and Bubbled AND gate
(Logic diagrams for De Morgan’s First Theorem is shown in fig.1(a)
Fig.1(a) Logic Diagrams for De Morgan’s First
Theorem
Q.27 The digital logic family which
has the lowest propagation delay time is
(A) ECL (B) TTL
(C) CMOS (D) PMOS
Ans: A
The digital logic
family which has the lowest propagation delay time is ECL
(Lowest propagation
delay time is possible in ECL because the transistors are used in difference
amplifier configuration, in which they are never driven into saturation and
thereby the storage time is eliminated).
Q.28 The device which changes from
serial data to parallel data is
(A) COUNTER (B) MULTIPLEXER
(C) DEMULTIPLEXER (D) FLIP-FLOP
Ans: C
The
device which changes from serial data to parallel data is demultiplexer.
(A demultiplexer
takes in data from one line and directs it to any of its N outputs depending on
the status of the select inputs.)
Q.29 A device which converts BCD to
Seven Segment is called
(A) Encoder (B) Decoder
(C) Multiplexer (D) Demultiplexer
Ans: B
A
device which converts BCD to Seven Segment is called DECODER.
(A decoder
coverts binary words into alphanumeric characters.)
Q.30 In a JK Flip-Flop, toggle means
(A)
Set Q = 1 and 
= 0.
(B)
Set Q = 0 and = 1.
(C)
Change the output to the opposite state.
(D)
No change in output.
Ans: C
In a JK Flip-Flop, toggle means
Change the output to the opposite state.
Q.31 The access time of
ROM using bipolar transistors is about
(A) 1 sec (B) 1 msec
(C) 1 μsec (D) 1 nsec.
Ans: C
The access time of ROM using bipolar transistors is about
1 
sec.
Q.32 The A/D converter
whose conversion time is independent of the number of bits is
(A) Dual slope (B) Counter type
(C) Parallel conversion (D) Successive approximation.
Ans: C
The A/D converter whose conversion time is independent of the Number of
bits is Parallel conversion.
(This type uses an array of comparators connected in parallel and
comparators compare the input voltage at a particular ratio of the reference
voltage).
Q.33 When signed numbers are used in
binary arithmetic, then which one of the following notations would have unique
representation for zero.
(A) Sign-magnitude. (B) 1’s complement.
(C) 2’s complement. (D)
9’s complement.
Ans: A
Q.34 The logic circuit given
below (Fig.1) converts a binary code 
into
(A)
Excess-3 code. (B) Gray code.
(C) BCD code. (D) Hamming code.
Ans: B
Gray code as
X1=Y1, X2=Y1 XOR
Y2 ,
X3=Y1 XOR Y2 XOR Y3
For Y1 Y2 Y3 X1 X2 X3
0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 1
0 1 1 0 1 0
Q.35 The logic circuit shown in the given
fig.2 can be minimised to
(A)
(B)
(C) (D)
Ans: D
As output of the logic circuit
is
Y=(X+Y’)’+(X’+(X+Y’)’)’
(X+Y’)’=X’Y Using DE Morgan’s
Now this is one of input of 2nd
gate.
F=(A+X’)’=A’X=[(X’Y)’.X]
=[(X+Y’)X]=X+XY’=X(Y’)
=X
Q.36 In digital ICs, Schottky transistors are preferred over normal transistors because of their
(A) Lower Propagation delay. (B) Higher Propagation
delay.
(C) Lower Power
dissipation. (D) Higher
Power dissipation.
Ans: A
Lower propagation
delay as shottky transistors reduce the storage time delay by preventing the
transistor from going deep into saturation.
Q.37 The following switching functions are
to be implemented using a Decoder:
The
minimum configuration of the decoder should be
(A) 2
– to – 4 line. (B) 3 – to – 8 line.
(C) 4 – to – 16 line. (D) 5 – to – 32 line.
Ans: C
4 to 16 line decoder as the minterms are ranging from 1 to 14.
Q.38 A 4-bit synchronous counter uses flip-flops with propagation delay times of 15 ns each. The maximum possible time required for change of state will be
(A)
15 ns. (B) 30 ns.
(C) 45 ns. (D) 60 ns.
Ans: A
15 ns because in
synchronous counter all the flip-flops change state at the same time.
Q.39 Words having 8-bits are to be stored into computer memory. The number of lines required for writing into memory are
(A)
1. (B) 2.
(C) 4. (D) 8.
Ans: D
Because 8-bit words
required 8 bit data lines.
Q.40 In
successive-approximation A/D converter, offset voltage equal to 
LSB is added to the
D/A converter’s output. This is done to
(A)
Improve the speed of operation.
(B)
Reduce the maximum quantization error.
(C)
Increase the number of bits at the output.
(D)
Increase the range of input voltage that can be converted.
Ans: B
Q.41 The decimal
equivalent of Binary number 11010 is
(A) 26. (B)
36.
(C)
16. (D) 23.
Ans: A
11010 = 1 X 24 + 1 X 2 3 + 0 X 22 + 1 X
21 = 26
Q.42 1’s complement representation of decimal number of -17 by using 8 bit representation is
(A) 1110 1110 (B) 1101 1101
(C) 1100 1100 (D) 0001 0001
Ans: A
(17)10 = (10001)2
In 8 bit = 00010001
1's Complement = 11101110
Q.43 The excess 3 code of decimal number 26 is
(A) 0100
1001 (B) 01011001
(C) 1000 1001 (D) 01001101
Ans: B
(26)10 in BCD is (
00100110 ) BCD
Add 011 to each BCD 01011001 for excess – 3
Q.44 How many AND gates are required to realize Y = CD+EF+G
(A)
4 (B) 5
(C) 3 (D) 2
Ans: D
To
realize Y = CD + EF + G
Two
AND gates are required (for CD & EF).
Q.45 How many select lines will a 16 to 1 multiplexer will have
(A) 4 (B) 3
(C) 5 (D) 1
Ans: A
In 16 to 1 MUX four select lines will be required to select
16 ( 24 ) inputs.
Q.46 How many flip flops are required to construct a decade counter
(A) 10 (B) 3
(C) 4 (D) 2
Ans: C
Decade counter counts 10 states from 0 to 9 (
i.e. from 0000 to 1001 )
Thus
four FlipFlop's are required.
Q.47 Which TTL logic gate is used for wired ANDing
(A) Open collector
output (B) Totem Pole
(C) Tri state output (D) ECL gates
Ans: A
Open collector output.
Q.48 CMOS circuits consume power
(A) Equal to TTL (B)
Less than TTL
(C) Twice of TTL (D) Thrice
of TTL
Ans: B
As in CMOS one device is ON &
one is Always OFF so power consumption is low.
Q.49 In a RAM, information can be stored
(A) By the user, number of times.
(B) By the user, only once.
(C) By the manufacturer, a number of times.
(D) By the manufacturer only once.
Ans: A
RAM is
used by the user, number of times.
Q.50 The hexadecimal
number for 
is
(A) 
(B)
(C) 
(D) 
Ans: A
(95.5)10 = (5F.8)16
Integer part Fractional part
16 95 0.5x16=8.0
16 5 15
0
5
Q.51 The octal
equivalent of 
is
(A) 
(B) 
(C) 
(D) 
Ans: C
(247)10
= (367)8
8 247
8 30 7
8 3 6
0
3
Q.52 The chief reason why digital computers use complemented subtraction is that it
(A) Simplifies
the circuitry.
(B)
Is a very simple process.
(C)
Can handle negative numbers easily.
(D)
Avoids direct subtraction.
Ans: C
Using complement method
negative numbers can also be subtracted.
Q.53 In a positive logic system, logic state 1 corresponds to
(A) positive voltage (B) higher voltage level
(C) zero voltage level (D)
lower voltage level
Ans: B
We decide two voltages levels for positive digital logic. Higher
voltage represents logic 1 & a lower voltage represents logic 0.
Q.54 The commercially available 8-input multiplexer integrated circuit in the TTL family is
(A) 7495.
(B) 74153.
(C) 74154. (D) 74151.
Ans: B
MUX integrated circuit
in TTL is 74153.
Q.55 CMOS circuits are extensively used for ON-chip computers mainly because of their extremely
(A) low power
dissipation. (B) high noise immunity.
(C) large packing density. (D)
low cost.
Ans: C
Because CMOS
circuits have large packing density.
Q.56 The MSI chip 7474 is
(A) Dual edge triggered JK flip-flop (TTL).
(B) Dual edge triggered D flip-flop (CMOS).
(C) Dual edge triggered D flip-flop (TTL).
(D) Dual edge triggered JK flip-flop (CMOS).
Ans: C
MSI chip 7474 dual edge triggered D Flip-Flop.
Q.57 Which of the following memories stores the most number of bits
(A) a 5M
8 memory. (B) a 1M 16 memory.
(C) a 
memory. (D) a 
memory.
Ans: A
5Mx8
= 5 x 220 x 8 = 40M (max)
Q.58 The process of entering data into a ROM is called
(A) burning in the ROM (B)
programming the ROM
(C) changing the ROM (D) charging the
ROM
Ans: B
The process of
entering data into ROM is known as programming the
Q.59 When the set of input data to an even parity generator is 0111, the output will be
(A) 1 (B) 0
(C) Unpredictable (D) Depends on the previous input
Ans: B
In even
parity generator if number of 1 is odd
then output will be zero.
1 1v
0
Q.60 The number 140 in
octal is equivalent to
(A) 
. (B)
.
(C) 
. (D) none of these.
Ans: A
(140)8 = (96)10
1 x 82 + 4 x 8 + 0x 1 = 64 + 32 =
96
Q.61 The NOR gate output will be low if the two inputs are
(A) 00 (B) 01
(C) 10 (D) 11
Ans: B, C, or D
O/P is low if any of the I/P is high
Q.62 Which of the following is the fastest logic?
(A) ECL (B) TTL
(C) CMOS (D) LSI
Ans: A
Q.63 How many flip-flops are required to construct mod 30 counter
(A) 5 (B) 6
(C) 4 (D) 8
Ans: A
Mod - 30 counter +/- needs 5 Flip-Flop
as 30 < 25
Mod - N counter
counts total ' N ' number of states.
To count 'N'
distinguished states we need minimum n FlipFlop's
as [N = 2n]
For eg. Mod 8 counter
requires 3 Flip-Flop's (8 = 23)
Q.64 How many address bits are required to represent a 32 K memory
(A) 10
bits. (B) 12 bits.
(C) 14 bits. (D) 16 bits.
Ans: D
32K = 25 x
210 = 215,
Thus 15 address bits are
required, Only 16 bits can address it.
Q.65 The number of control lines for 16 to 1 multiplexer is
(A) 2. (B) 4.
(C) 3. (D) 5.
Ans: B
As
16 = 24, 4 Select lines are required.
Q.66 Which of following requires refreshing?
(A) SRAM. (B) DRAM.
(C) ROM. (D) EPROM.
Ans: B
Q.67 Shifting a register content to left by one bit position is equivalent to
(A) division by two. (B)
addition by two.
(C) multiplication by
two. (D) subtraction
by two.
Ans:C
Q.68 For JK flip flop with J=1, K=0, the output after clock pulse will be
(A) 0. (B) 1.
(C) high impedance. (D) no change.
Ans: B
Q.69 Convert decimal 153
to octal. Equivalent in octal will
be
(A) 
. (B)
.
(C) 
. (D) none of these.
Ans: A
(153)10 = (231)8
8 153 1
8 19 3
8 2 2
Q.70 The
decimal equivalent of 
is
(A) 12 (B) 16
(C) 18 (D) 20
Ans: A
(1100)2 = (12)10
Q.71 The
binary equivalent of 
is
(A) 1010
1111 (B) 1111 1010
(C) 10110011 (D) none of these
Ans: B
(FA)16 = (11111010)10
Q.72 The output of SR flip flop when S=1, R=0 is
(A) 1 (B) 0
(C) No change (D) High impedance
Ans: A
As for the SR
flip-flop S=set input R=reset input ,when S=1, R=0, Flip-flop will be set.
Q.73 The number of flip flops contained in IC 7490 is
(A) 2.
(B) 3.
(C) 4. (D) 10.
Ans: A
Q.74 The number of control lines for 32 to 1 multiplexer is
(A) 4. (B) 5.
(C) 16. (D) 6.
Ans: B
The number of control
lines for 32 (25) and to select one input among them total 5 select lines are required.
Q.75 How many two-input AND and OR gates are required to realize Y=CD+EF+G
(A) 2,2. (B) 2,3.
(C) 3,3. (D) none of these.
Ans: A
Y=CD+EF+G
Number of two input AND gates=2
Number of two input OR gates = 2
One OR gate to OR CD and EF and
next to OR of G & output of first OR gate.
Q.76 Which of following can not be accessed randomly
(A) DRAM. (B) SRAM.
(C) ROM. (D) Magnetic tape.
Ans: D
Magnetic tape can only
be accessed sequentially.
Q.77 The excess-3 code of decimal 7 is represented by
(A) 1100. (B)
1001.
(C) 1011. (D)
1010.
Ans: D
An
excess 3 code is always equal to the binary code +3
Q.78 When an input signal A=11001 is applied to a NOT gate serially, its output signal is
(A) 00111. (B) 00110.
(C) 10101. (D) 11001.
Ans: B
As A=11001 is serially applied
to a NOT gate, first input applied will be LSB 00110.
Q.79 The result of adding
hexadecimal number A6 to 3A is
(A) DD. (B)
E0.
(C) F0. (D) EF.
Ans:
B
Q.80 A universal logic gate is one, which can be used to generate any logic function. Which of the following is a universal logic gate?
(A)
OR (B) AND
(C) XOR (D) NAND
Ans: D
NAND can generate any logic function.
Q.81 The logic 0 level of a CMOS logic device is approximately
(A) 1.2 volts (B) 0.4 volts
(C) 5 volts (D) 0 volts
Ans: D
CMOS logic low level is 0 volts
approx.
Q.82 Karnaugh map is used for the purpose of
(A) Reducing the electronic circuits used.
(B) To map the given Boolean
logic function.
(C) To minimize the terms in a Boolean
expression.
(D) To maximize the terms of a given a Boolean
expression.
Ans: C
Q.83 A full adder logic circuit will have
(A) Two
inputs and one output.
(B) Three inputs and three outputs.
(C) Two inputs and two outputs.
(D) Three inputs and two outputs.
Ans:
D
A full adder circuit will add two bits and it will also
accounts the carry input generated in the previous stage. Thus three inputs and
two outputs (Sum and Carry) are there.
Q.84 An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50ns. The frequency of the input signal which can be used for proper operation of the counter is approximately
(A)
1 MHz. (B) 500 MHz.
(C) 2 MHz. (D) 4 MHz.
Ans: A
Maximum time taken for all flip-flops to stabilize is 75ns x 8 + 50 = 650ns. Frequency of operation must be less than 1/650ns = 1.5 MHz.
Q.85 The output of a JK flipflop with asynchronous preset and clear inputs is ‘1’. The output can be changed to ‘0’ with one of the following conditions.
(A) By applying J = 0, K =
0 and using a clock.
(B) By applying J = 1, K = 0 and using the clock.
(C) By applying J = 1, K = 1 and using the clock.
(D) By applying a synchronous preset input.
Ans: C
Preset state of JK Flip-Flop =1
With
J=1 K=1 and the clock next state will be complement of the present state.
Q.86 The information in ROM is stored
(A) By the user any
number of times.
(B) By the manufacturer
during fabrication of the device.
(C)
By the user using
ultraviolet light.
(D)
By the user once and
only once.
Ans: B
Q.87 The conversation speed of an analog to digital converter is maximum with the following technique.
(A) Dual slope AD converter.
(B) Serial comparator AD converter.
(C) Successive approximation AD converter.
(D) Parallel comparator AD converter.
Ans: D
Q.88 A weighted resistor digital to analog converter using N bits requires a total of
(A) N precision resistors. (B) 2N precision resistors.
(C) N + 1 precision resistors. (D) N – 1 precision resistors.
Ans: A
Q.89 The 2’s complement of
the number 1101110 is
(A) 0010001. (B)
0010001.
(C) 0010010. (D) None.
Ans: C
1’s complement of 1101110 is = 0010001
Thus 2’s complement of 1101110 is = 0010001 + 1 = 0010010
Q.90 The decimal equivalent of Binary number 10101 is
(A) 21 (B) 31
(C) 26 (D) 28
Ans: A
1x24
+ 0x23 +1x22 +0x21 + 1x20
= 16 + 0 + 4 + 0 + 1 = 21.
Q.91 How many two input AND gates and two input OR gates are required to realize
Y = BD+CE+AB
(A) 1, 1 (B) 4, 2
(C) 3, 2 (D) 2, 3
Ans: A
There are three product terms, so three AND gates of two inputs are required.
As only two input OR gates are available, so two OR gates are required to get the logical sum of three product terms.
Q.92 How many select lines will a 32:1 multiplexer will have
(A) 5.
(B) 8.
(C) 9. (D) 11.
Ans: A
For 32 inputs, 5 select lines will be required, as 25 = 32.
Q.93 How many address bits are required to represent 4K memory
(A) 5 bits. (B) 12 bits.
(C) 8 bits. (D) 10 bits.
Ans: B
For representing 4K memory, 12 address bits are required as
4K = 22 x 210 = 212 (1K = 1024 = 210)
Q.94 For JK flipflop J = 0, K=1, the output after clock pulse will be
(A) 1. (B) no change.
(C) 0. (D) high impedance.
Ans: C
J=0, K=1, these inputs will reset the flip-flop after the clock pulse. So whatever be the previous output, the next state will be 0.
Q.95 Which of following are known as universal gates
(A) NAND & NOR. (B) AND & OR.
(C) XOR & OR. (D) None.
Ans: A
NAND & NOR are known as universal gates, because any digital circuit can be realized completely by using either of these two gates.
Q.96 Which of the following memories stores the most number of bits
(A) 
memory. (B) 
memory.
(C) 
memory. (D) 
memory.
Ans: C
32M x 8 stores most number of bits
25 x 220 = 225 (1M = 220 = 1K x 1K = 210 x 210)
Q.97 Which of following consume minimum power
(A) TTL. (B) CMOS.
(C) DTL. (D) RTL.
Ans: B
CMOS consumes minimum power as in CMOS one p-MOS & one n-MOS transistors are connected in complimentary mode, such that one device is ON & one is OFF.
.
.
.
) (Since 
= 
.0 + C.
.
+
C + 
+ A